Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
As is well-known, integrated circuits are typically manufactured in batches, and these batches usually contain a plurality of semiconductor wafers within and upon which integrated circuits are formed through a variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, planarizing and so on.
Completed wafers are tested to determine which die, or integrated circuits, on the wafer are capable of operating according to predetermined specifications. In this way, integrated circuits that cannot perform as desired are not packaged, or otherwise incorporated into finished products.
It is common to manufacture integrated circuits on roughly circular semiconductor substrates, or wafers. Further, it is common to form such integrated circuits so that conductive regions disposed on, or close to, the uppermost layers of the integrated circuits are available to act as terminals for connection to various electrical elements disposed in, or on, the lower layers of those integrated circuits. In testing, these conductive regions are commonly contacted with a probe card.
It is common to mount the wafer on a moveable chuck, which is used to achieve accurate positioning and to hold the wafer in place during testing. Often, a device such as a flexible membrane probe is brought into contact with a chuck-mounted wafer via a gasket seal. However, there is a tendency for the wafer to conform to the planar profile of the chuck, as the pressure that forms the contacts between the membrane and the wafer is supplied by the vertical movement of the chuck and the downward pressure of the vacuum. In full-wafer test, small irregularities in the planar profile of the chuck can adversely affect the ability of the wafer and the tester interface to form consistent electrical connections. The significance of these irregularities is amplified at higher pin counts and larger diameters.
What is needed are methods and apparatus that enable the wafer to achieve coplanarity with the tester interface.